AI-powered tools
for FPGA and SoC development.
Tools built with AI, and tools that use it: describe what you need and get synthesizable RTL, rendered from verified templates, analysed with Yosys and simulated with Icarus Verilog before you ever see it. Free while in beta.
Tools
Everything here runs server-side and is free to use: no sign-up and no key, one run every 30 seconds. Requests are logged to improve the service, so keep confidential designs out of them (see the terms of use).
filter-designer
BetaIIR (Butterworth, Chebyshev, elliptic, Bessel) or FIR (windowed sinc) from a specification to fixed-point Verilog with a self-checking testbench. The backend simulates the RTL under Icarus Verilog against a bit-exact model, then plots the realized response over the design.
axi-slave
BetaDescribe the peripheral in plain English and get an AXI4-Lite register-bank slave. A language model names the registers and decides which ones the processor writes and which it only reads; the Verilog itself comes from a fixed template, and Yosys elaborates and technology-maps it before you see it.
MCP servers
Open-source MCP
servers that give an AI agent hands-on tools for FPGA work. Download the zip, unpack it
and run install.sh: it creates a Python environment and registers the server
with Claude Code. They are standard stdio servers, so Copilot or any other MCP client
works too (see the README inside).
redpitaya
Open sourceLets an agent drive a Red Pitaya STEMlab 125-14 over SCPI: configure the signal generator with standard or arbitrary waveforms and run trigger-based acquisitions at a chosen sample rate, without writing a line of SCPI. The agent can stimulate a design and measure what comes back.
- connect
- generator_set
- generator_set_arbitrary
- generator_output
- set_sample_rate
- acquire
unzip redpitaya-mcp.zip && bash redpitaya-mcp/install.shbiquad2rtl
Open sourceDesigns a second-order IIR filter from a type, a cutoff frequency and a quality factor, quantizes the coefficients to fixed point and emits a synthesizable Verilog biquad with its instantiation template. The agent can also characterize a filter (poles, zeros, -3 dB point) before committing to RTL.
- generate_biquad_rtl
- characterize_biquad
unzip biquad2rtl-mcp.zip && bash biquad2rtl/install.shSkills
Agent skills that package an FPGA workflow — the steps, the conventions and the
checks — so an agent can follow it end to end in your own project. Each one is a
single SKILL.md: take it as is or keep the parts you need.
add-biquad-filter
Open sourceAsk for a filter against your own RTL — "low-pass this input at 2 kHz and give me the filtered output" — and the agent designs the biquad with biquad2rtl, reads the host module and wires a ready-to-synthesize instance into it, matching clock, reset, widths, fixed-point format and the valid handshake. Needs the biquad2rtl MCP server.
more skills
Coming soonMore skills are being written up. They will be published here, ready to download.
Bringing AI workflows into your FPGA designs?
If you need to integrate AI into your FPGA development flow — agents that generate and verify RTL, MCP servers for your own tools and instruments, or skills tailored to your team's conventions — get in touch and we will look at it together.
How it works
The same pipeline behind every tool on this site.
You describe or paste
A filter specification, or a peripheral in plain English.
Templates, not vibes
The model only chooses parameters and names; the Verilog comes from templates that are verified once and reused every time.
You get something usable
A synthesizable module with its instantiation template, a Yosys resource estimate for your device and, for filters, a bit-exact simulation — not a chat transcript.
Soon: real silicon
The verification bench builds the design, runs it on hardware and measures what it actually does.
Built in the open, written up on the blog
Every tool here started as an article on controlpaths.com — remote FPGA verification, AI-generated testbenches, and giving an agent control of a real instrument bench over MCP.