AI · FPGA · SoC

AI-powered tools
for FPGA and SoC development.

Tools built with AI, and tools that use it: describe what you need and get synthesizable RTL, rendered from verified templates, analysed with Yosys and simulated with Icarus Verilog before you ever see it. Free while in beta.

Tools #

Everything here runs server-side and is free to use: no sign-up and no key, one run every 30 seconds. Requests are logged to improve the service, so keep confidential designs out of them (see the terms of use).

filter-designer

Beta

IIR (Butterworth, Chebyshev, elliptic, Bessel) or FIR (windowed sinc) from a specification to fixed-point Verilog with a self-checking testbench. The backend simulates the RTL under Icarus Verilog against a bit-exact model, then plots the realized response over the design.

Design a filter →

axi-slave

Beta

Describe the peripheral in plain English and get an AXI4-Lite register-bank slave. A language model names the registers and decides which ones the processor writes and which it only reads; the Verilog itself comes from a fixed template, and Yosys elaborates and technology-maps it before you see it.

Generate a slave →

How it works #

The same pipeline behind every tool on this site.

You describe or paste

A filter specification, or a peripheral in plain English.

Templates, not vibes

The model only chooses parameters and names; the Verilog comes from templates that are verified once and reused every time.

You get something usable

A synthesizable module with its instantiation template, a Yosys resource estimate for your device and, for filters, a bit-exact simulation — not a chat transcript.

Soon: real silicon

The verification bench builds the design, runs it on hardware and measures what it actually does.

MCP servers #

Open-source MCP servers that give an AI agent hands-on tools for FPGA work. Download the zip, unpack it and run install.sh: it creates a Python environment and registers the server with Claude Code. They are standard stdio servers, so Copilot or any other MCP client works too (see the README inside).

redpitaya

Open source

Lets an agent drive a Red Pitaya STEMlab 125-14 over SCPI: configure the signal generator with standard or arbitrary waveforms and run trigger-based acquisitions at a chosen sample rate, without writing a line of SCPI. The agent can stimulate a design and measure what comes back.

  • connect
  • generator_set
  • generator_set_arbitrary
  • generator_output
  • set_sample_rate
  • acquire
unzip redpitaya-mcp.zip && bash redpitaya-mcp/install.sh
Download .zip GitHub

biquad2rtl

Open source

Designs a second-order IIR filter from a type, a cutoff frequency and a quality factor, quantizes the coefficients to fixed point and emits a synthesizable Verilog biquad with its instantiation template. The agent can also characterize a filter (poles, zeros, -3 dB point) before committing to RTL.

  • generate_biquad_rtl
  • characterize_biquad
unzip biquad2rtl-mcp.zip && bash biquad2rtl/install.sh
Download .zip GitHub

Skills #

Agent skills that package an FPGA workflow — the steps, the conventions and the checks — so an agent can follow it end to end in your own project. Each one is a single SKILL.md: take it as is or keep the parts you need.

add-biquad-filter

Open source

Ask for a filter against your own RTL — "low-pass this input at 2 kHz and give me the filtered output" — and the agent designs the biquad with biquad2rtl, reads the host module and wires a ready-to-synthesize instance into it, matching clock, reset, widths, fixed-point format and the valid handshake. Needs the biquad2rtl MCP server.

Download SKILL.md

more skills

Coming soon

More skills are being written up. They will be published here, ready to download.

AI for FPGA development, on your own infrastructure #

The free tools above log their requests, so they are no place for confidential designs. For a company the answer is the same pipeline running inside its own network: a local model, MCP servers for its tools and instruments, skills that follow its conventions and AI checks in its CI/CD pipelines, with no code leaving the building.

private-ai-pilot #

Everything you see on this site, deployed inside your company. A local language model, MCP servers for your tools, skills that follow your team's conventions and a knowledge base built from your own IP, datasheets and past projects. At the end your engineers are generating, reviewing and verifying RTL with AI, on infrastructure you control.

  • hardware sizing
  • model selection
  • installation
  • simulation flow
  • training

custom-mcp-server #

Give your AI agent hands on your lab. MCP servers that connect agents to your instruments, boards and tools: oscilloscopes and generators over SCPI, JTAG debug, Vivado and Quartus Tcl flows, or your in-house scripts. The agent stimulates a design, measures the response and closes the loop, as the Red Pitaya server above does. Built on the open MCP standard, so it is not tied to one vendor: the same server works with any MCP-capable agent.

  • source code
  • documentation
  • tests

team-skills-pack #

Teach the agent how your team works. Coding style, reset and clocking rules, handshake conventions, project structure and review checklists, packaged as agent skills so Claude Code, Copilot or any other agent follows them end to end in your own projects.

  • tested on your codebase
  • any agent

ai-in-ci-cd #

Put the agent in your pipeline, not only in the editor. On every merge request it reviews the RTL against your rules, writes or extends testbenches, runs simulation and synthesis checks and comments the results back on the change. Everything runs on your own runners with a local model, so the code never leaves your servers.

  • RTL review
  • testbench generation
  • regression reports
  • self-hosted runners
See the pipeline step by step →

How an engagement works #

A 30-minute call

Free and under NDA if you need it. We look at your flow and at the repetitive task that eats most of your engineers' hours.

Flow assessment

One or two days reviewing how your team designs and verifies, with a written report of what is worth automating and what is not.

Fixed-scope proposal

Concrete deliverables, a closed scope and a date. No open-ended hours.

Delivery on your code

A live demo on your own designs, the source of everything built for you, and optional ongoing support and model updates.

Get in touch

Not sure where to start? #

Book a free 30-minute call and we will look at your flow together. Write to the address on the right with a couple of lines about your team and the tools you use.

info @ the domain you are

Built in the open, written up on the blog

Every tool here started as an article on controlpaths.com — remote FPGA verification, AI-generated testbenches, and giving an agent control of a real instrument bench over MCP.

Read the blog Source on GitHub