TOOL · BETA

filter-designer

Specify an IIR or FIR filter and get fixed-point Verilog with a self-checking testbench. The backend designs the coefficients, renders the RTL from templates, runs the testbench under Icarus Verilog against a bit-exact model of the same arithmetic, and measures the realized response at a set of test tones.

Specification

IIR FIR

Response

Sample rate f_s (Hz)

Cutoff f_c (Hz)

IIR

Family

Order

Realized as a cascade of Direct Form I biquads, one pipeline register per section.

Fixed point

Data width (bits)

Fractional bits

Format: Q11.20

Resource estimate for

Yosys technology-maps the generated RTL for this family (adds a few seconds).

Module name (optional)

Run the testbench under Icarus Verilog

I accept the terms of use.

Free to use, one run every 30 seconds. Every request and its result are logged and may be used to improve the service, so don't submit confidential designs.

Set a specification and press Design & verify.
You get the Bode plot, the coefficients, the RTL, the testbench and the simulation verdict.

Self-checking testbench. It instantiates the filter exactly as the instantiation template does, streams three test tones from tone_*.mem and compares every output sample with expected_*.mem, produced by the bit-exact software model.

Simulator log