TOOL · BETA

axi-slave

Describe what your peripheral does and get an AXI4-Lite register-bank slave in two steps. First a language model reads the description and proposes the register map — names, which registers the processor writes and which it only reads, reset values. You add, remove, rename and reorder registers until the map is right. Then the RTL is rendered from a fixed, verified template — the model never writes Verilog — and the backend elaborates and technology-maps it with Yosys before showing it to you.

Peripheral

What does the peripheral do?

The model uses this to propose the registers and their access. Leave it empty to start from generic rw_reg0/ro_reg0 names and edit them yourself.

Model decides I set them

The model picks the fewest registers that cover the description (up to 16 of each kind).

Module name (optional)

Address width (optional)

Analyse for

Used in step 2: Yosys elaborates the generated slave, applies the linter rules and technology-maps it for this family.

I accept the terms of use.

Free to use, one proposal and one generation every 30 seconds. Every request and its result are logged and may be used to improve the service, so don't describe confidential designs.

Describe the peripheral and press Propose registers.
The proposed map appears here for you to edit; Generate RTL then renders the Verilog slave, its instantiation template, a C header with the offsets, and runs the Yosys analysis.