TOOL · BETA

axi-slave

Describe what your peripheral does and get an AXI4-Lite register-bank slave. A language model reads the description and proposes the register map — names, which registers the processor writes and which it only reads, reset values — but never writes a line of Verilog: the RTL comes from a fixed, verified template, and the backend elaborates and technology-maps it with Yosys before showing it to you.

Peripheral

The model uses this to name the registers and decide their access. Leave it empty for generic rw_reg0/ro_reg0 names.

Register count

The model picks the fewest registers that cover the description (up to 16 of each kind).

Yosys elaborates the generated slave, applies the linter rules and technology-maps it for this family.

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Describe the peripheral and press Generate & analyse.
You get the register map, the Verilog slave with its instantiation template, a C header with the offsets, and the Yosys analysis of the generated module.