Any model can write Verilog.
Almost none can be trusted.
Free tools that check and generate synthesizable RTL — built on a decade of FPGA work and a rulebook of vendor-specific mistakes that language models make over and over again.
Tools
Everything here runs server-side and is free to use while it is in beta. No sign-up, no upload of your project — one module at a time.
rtl-lint
BetaPaste Verilog written by a language model and get the synthesis problems before Vivado or Quartus finds them: inferred latches, asynchronous resets where the vendor forbids them, blocking assignments in sequential blocks, silent width truncation, unreachable FSM states.
filter-designer
BetaIIR (Butterworth, Chebyshev, elliptic, Bessel) or FIR (windowed sinc) from a specification to fixed-point Verilog with a self-checking testbench. The backend simulates the RTL under Icarus Verilog against a bit-exact model, then plots the realized response over the design.
axi-slave
BetaDescribe the peripheral in plain English and get an AXI4-Lite register-bank slave. A language model names the registers and decides which ones the processor writes and which it only reads; the Verilog itself comes from a fixed template, and Yosys elaborates and technology-maps it before you see it.
Need this inside your own flow?
The same engine is available as a keyed REST API and as an MCP server, so an agent in Claude Code or Copilot can design, verify and drop the finished package — RTL, testbench with vectors, Markdown report, plots and a Makefile — straight into your project folder. Tell us what you want to build and we will set you up with a key.
How it works
The same pipeline behind every tool on this site.
You describe or paste
A filter specification, a peripheral in plain English, or a Verilog module you did not write by hand.
Rules, not vibes
Checks run against a curated rulebook of real synthesis failures, per vendor and per device family.
You get something usable
Annotated findings or a synthesizable module with its testbench — not a chat transcript.
Soon: real silicon
The verification bench builds the design, runs it on hardware and measures what it actually does.
Built in the open, written up on the blog
Every tool here started as an article on controlpaths.com — remote FPGA verification, AI-generated testbenches, and giving an agent control of a real instrument bench over MCP.